1. Field of the Invention
The present invention relates generally to automatic test vector generation and specifically to a method of generating input vectors for testing electronic circuits.
2. Description of the Prior Art
It is common practice to test every circuit after manufacture to see if any manufacturing defects are present. A digital circuit may be tested by applying a sequence of binary vectors and observing the circuit's response. The test vectors are designed to expose the manufacturing defects. Manufacturing defects are typically modeled on the logic gate description of the digital circuit. Chip defects are commonly modeled as a node in the circuit stuck-at logic 0 or stuck-at logic 1. Automatic test vector generation programs analyze the circuit and attempt to excite a stuck-at fault and propagate the faulty effect to an observable primary output (PO).
The field of test generation is covered in the book by Abramovici, Breuer and Friedman (Digital Systems Testing and Testable Design, Computer Science Press, New York, N.Y., 1990, ISBN 0-7167-8179-4).
Most automatic test generators employ systematic search methods to find a binary vector that satisfies the requirements of a test vector. The search methods search over an enormous space of binary vectors and vector sequences. A variety of techniques are provided to speed up the search methods. However, due to the enormity of search space, conventional test generator schemes fail to generate a test sequence that will detect a large number of faults in very large scale integrated (VLSI) circuits. As a consequence, the test sequences generated by such test generators fail to identify many defective chips resulting in poor quality in shipped parts.